A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL

This work presents a delta-sigma modulator free in-loop-bandwidth spread-spectrum clock generator. The proposed charge-based discrete-time loop filter with a digital-tocurrent converter enables wide range spread-spectrum frequency modulation with significantly relaxed PVT sensitivity. A correlated double sampling technique is leveraged to minimize 1/f noise in the proposed discrete-time loop filter. This work achieves 3.2% spread-spectrum modulation range and 26.51dB spectrum attenuation at 352MHz output frequency. A 142% change in KVCO results in less than 298ppm modulation range error. Implemented in a 0.18μm CMOS, this work achieves 951fsrms period jitter while consuming 9.93mW with a 1.8V supply.